P-/metal floating gate non-volatile storage element

ABSTRACT

Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

PRIORITY

This application claims the benefit of U.S. Provisional Application No.61/466,295, entitled “P−/Metal Floating Gate Non-Volatile StorageElement,” by Lee et al., filed on Mar. 22, 2011, incorporated herein byreference.

BACKGROUND

1. Field

This disclosure relates to non-volatile memory.

2. Description of the Related Art

Semiconductor memory has become increasingly popular for use in variouselectronic devices. For example, non-volatile semiconductor memory isused in cellular telephones, digital cameras, personal digitalassistants, mobile computing devices, non-mobile computing devices andother devices. Electrically Erasable Programmable Read Only Memory(EEPROM) and flash memory are among the most popular non-volatilesemiconductor memories. With flash memory, also a type of EEPROM, thecontents of the whole memory array, or of a portion of the memory, canbe erased in one step, in contrast to the traditional, full-featuredEEPROM.

Both traditional EEPROM and flash memory utilize a floating gate that ispositioned above and insulated from a channel region in a semiconductorsubstrate. Typically, a “tunnel oxide” insulates the floating gate fromthe channel. The floating gate is positioned between the source anddrain regions. A control gate is provided over and insulated from thefloating gate. The threshold voltage (V_(TH)) of the transistor thusformed is controlled by the amount of charge that is retained on thefloating gate. That is, the minimum amount of voltage that must beapplied to the control gate before the transistor is turned on to permitconduction between its source and drain is controlled by the level ofcharge on the floating gate.

Some EEPROM and flash memory devices have a floating gate that is usedto store two ranges of charges and, therefore, the memory element can beprogrammed/erased between two states, e.g., an erased state and aprogrammed state. Such a flash memory device is sometimes referred to asa binary flash memory device because each memory element can store onebit of data.

A multi-state (also called multi-level) flash memory device isimplemented by identifying multiple distinct allowed/valid programmedthreshold voltage ranges. Each distinct threshold voltage rangecorresponds to a predetermined value for the set of data bits encoded inthe memory device. For example, each memory element can store two bitsof data when the element can be placed in one of four discrete chargebands corresponding to four distinct threshold voltage ranges.

One issue of concern is data retention. Over time, charge on thefloating gate may be lost or gained across the tunnel oxide, therebychanging the threshold voltage. It is also possible to lose or gaincharge across the insulator the separates the floating gate from thecontrol gate. For some devices, losing or gaining charge across thetunnel oxide is a greater problem of these two effects.

Another phenomenon that presents problems is stress induced leakagecurrents (SILC). Programming and erasing memory cells may stress theinsulator below the floating gates. This stress may result in a greaterleakage current through the insulator.

Another problem is program saturation. When a high program voltage isapplied to the control gate, the tunneling of electrons should occurthrough the tunnel oxide between the substrate and the floating gate.However, tunneling should not occur through the inter-gate oxide betweenthe control gate and the floating gate. If, however, electrons do tunnelthrough the inter-gate oxide then programming saturates.

For some memory arrays, with continued scaling the individual thresholdvoltage ranges that define each state are getting wider. If theindividual threshold voltage ranges are wider, then the margin betweenthe threshold voltage ranges becomes smaller (assuming the same overallwidth for all threshold voltage ranges). The smaller margin betweenthreshold voltage distributions makes data retention a more significantissue.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top view of a NAND string.

FIG. 1B is an equivalent circuit diagram of the NAND string of FIG. 1A.

FIG. 2A is a circuit diagram of three NAND strings with associated wordlines.

FIG. 2B is a top view of the three NAND strings and word lines.

FIG. 3 depicts a cross-sectional view of a NAND string formed on asubstrate.

FIG. 4 illustrates a non-volatile storage device that may include one ormore memory die or chips.

FIG. 5 depicts an exemplary structure of memory cell array.

FIG. 6 is a block diagram of an individual sense block.

FIG. 7 depicts example threshold voltage distributions for states ofmemory cells in which there are eight states.

FIG. 8A depicts one embodiment of non-volatile storage elements andtransistors.

FIG. 8B is a view along a portion of line B-B′ from FIG. 8A for oneembodiment.

FIG. 8C is a view along line C-C′ from FIG. 8A.

FIG. 8D depicts one embodiment in which the transistor gates are mostlyN+ polysilicon.

FIG. 8E depicts a view along line D-D′ from FIG. 8D.

FIG. 8F depicts one embodiment in which transistor gates have a metalregion at the top and an N+ region at the bottom.

FIG. 8G depicts one embodiment in which floating gates have an etch stopregion between a p− region and a metal region, and transistor gates areN+.

FIG. 9A depicts one embodiment in which the floating gates have aninverted T-shape.

FIG. 9B shows a perspective for one embodiment along line B-B′ of FIG.8A.

FIGS. 10A, 10B, 10C, 11A, 11B, 11C, 12A, 12B, 12C depict energy banddiagrams.

FIGS. 13A-13C depict band diagrams for embodiments of memory cellshaving P−/Metal floating gates.

FIG. 14 is a flowchart of one embodiment of a process of forming amemory array with memory cells having P−/metal floating gates andtransistors having P−/metal gates.

FIG. 15A is a flowchart one embodiment of a process of formingtransistors and non-volatile storage elements in which the transistorsare p− semiconductor near the gate oxide and metal away from the gateoxide.

FIG. 15B depicts further details of one embodiment of a process forforming non-volatile storage elements and transistors in which thetransistors are p− semiconductor near the gate oxide and metal away fromthe gate oxide.

FIGS. 16A, 16B, 16C, 16D, and 16E depict results after various steps ofthe process of FIG. 15B.

FIG. 17A is a flowchart one embodiment of a process of formingtransistors and non-volatile storage elements in which the transistorsare N+ semiconductor near the gate oxide and metal away from the gateoxide.

FIG. 17B depicts one embodiment of a process for forming memory array inwhich metal is used to fill the etched away portions of metal wheretransistor gates are to be formed.

FIGS. 18A and 18B show results after various steps the process of FIG.17A.

FIG. 19 is a flowchart one embodiment of a process of formingtransistors and non-volatile storage elements in which an etch stoplayer is used.

FIGS. 20A, 20B, and 20C show results after various steps the process ofFIG. 19.

DETAILED DESCRIPTION

With continued scaling of memory arrays, such as NAND flash, theprogrammed states may become wider; therefore, this leaves smallermargins for data retention and SILC. Furthermore, scaling the tunneloxide (e.g., reducing the tunnel oxide thickness) may not be possibledue to necessary margins for data retention and degradation related toSILC. Technology disclosed herein includes a “P−/Metal” floating gate ina non-volatile storage device. The P−/Metal floating gate may improvedata retention margins while providing about the same coupling ratio asa floating gate that is entirely “N+”. Having a good coupling ratio maymean that programming speed is not sacrificed. Improved data retentionmay, in effect, allow a greater margin between programmed states and/ormay enable reduction of tunnel oxide thickness.

Non-volatile storage elements having a P−/Metal floating gate aredisclosed herein. The floating gate may have a P− region near the tunneloxide, and may have a metal region near the control gate. In someembodiments, the metal has a high electron work function. This may helpto reduce program saturation. Example metals for the floating gateinclude, but are not limited to, W, WN, TiN, TaN, Mo, and TiO.

In some embodiments, a P− region near the tunnel oxide helps providegood data retention. In some embodiments, a metal region near thecontrol gate helps to achieve a good coupling ratio between the controlgate and floating gate. Therefore, programming of non-volatile storageelements is efficient. Also embodiments erase the non-volatile storageelements efficiently. In some embodiments, having a P− region near thetunnel oxide (as opposed to a strongly doped p-type semiconductor)improves erase efficiency relative to P+.

Note that techniques for fabricating non-volatile storage devices arecompatible with those for fabricating transistors. Also note that forsome transistors, it might not be desirable to have a P− region near thegate oxide. Techniques are described herein for efficiently fabricatingmemory cells with P− regions near the tunnel oxide, along withtransistors with N+ regions near the gate oxide.

Example Memory System and Operation

One example of a memory system suitable for implementing embodimentsuses a NAND flash memory architecture, which includes connectingmultiple transistors in series between two select gates. The transistorsconnected in series and the select gates are referred to as a NANDstring. FIG. 1A is a top view showing one NAND string. FIG. 1B is anequivalent circuit thereof. The NAND string includes four transistors,100, 102, 104 and 106, in series and sandwiched between a first selectgate 120 and a second select gate 122. Select gate 120 gates the NANDstring connection to bit line 126. Select gate 122 gates the NAND stringconnection to source line 128. Select gate 120 is controlled by applyingthe appropriate voltages to control gate 120CG. Select gate 122 iscontrolled by applying the appropriate voltages to control gate 122CG.Each of the transistors 100, 102, 104 and 106 has a control gate and afloating gate. Transistor 100 has control gate 100CG and floating gate100FG. Transistor 102 includes control gate 102CG and floating gate102FG. Transistor 104 includes control gate 104CG and floating gate104FG. Transistor 106 includes a control gate 106CG and floating gate106FG. Control gate 100CG is connected to (or is) word line WL3, (whereWL denotes “word line”), control gate 102CG is connected to WL2, controlgate 104CG is connected to WL1, and control gate 106CG is connected toWL0. In one embodiment, transistors 100, 102, 104 and 106 are eachstorage elements, also referred to as memory cells. In otherembodiments, the storage elements may include multiple transistors ormay be different than depicted. Select gate 120 is connected to selectline SGD. Select gate 122 is connected to select line SGS.

A typical architecture for a flash memory system using a NAND structurewill include several NAND strings. Each NAND string is connected to thesource line by its source select gate controlled by select line SGS andconnected to its associated bit line by its drain select gate controlledby select line SGD. Each bit line and the respective NAND string(s) thatare connected to that bit line via a bit line contact comprise thecolumns of the array of memory cells. Bit lines are shared with multipleNAND strings. Typically, the bit line runs on top of the NAND strings ina direction perpendicular to the word lines and is connected to one ormore sense amplifiers.

FIG. 2A shows three NAND strings 202, 204 and 206 of a memory arrayhaving many more NAND strings. Each of the NAND strings of FIG. 2Aincludes two select transistors and four memory cells. For example, NANDstring 202 includes select transistors 220 and 230, and memory cells222, 224, 226 and 228. NAND string 204 includes select transistors 240and 250, and memory cells 242, 244, 246 and 248. Each NAND string isconnected to the source line by its select transistor (e.g., selecttransistor 230 and select transistor 250). A selection line SGS is usedto control the source side select gates. The various NAND strings areconnected to respective bit lines by select transistors 220, 240, etc.,which are controlled by select line SGD. In other embodiments, theselect lines do not necessarily need to be in common. Word line WL3 isconnected to the control gates for memory cell 222 and memory cell 242.Word line WL2 is connected to the control gates for memory cell 224,memory cell 244, and memory cell 252. Word line WL1 is connected to thecontrol gates for memory cell 226 and memory cell 246. Word line WL0 isconnected to the control gates for memory cell 228 and memory cell 248.As can be seen, each bit line and the respective NAND string comprisesthe columns of the array of memory cells. The word lines (WL3, WL2, WL1and WL0) comprise the rows of the array.

FIG. 2B is a top view of a portion of an array of NAND flash memorycells. The array includes bit lines 250 and word lines 252. Shallowtrench isolation (STI) structures 245 are depicted between the bit lines250 (note the bit lines are not at the same level as the STI structures245). Note that FIG. 2B does not show all of the other details of theflash memory cells. Note that a NAND string can have fewer or morememory cells than depicted in FIGS. 2A and 2B. For example, some NANDstrings will include eight memory cells, 16 memory cells, 32 memorycells, 64 memory cells, 128 memory cells, etc. The discussion herein isnot limited to any particular number of memory cells in a NAND string.Furthermore, a wordline can have more or fewer memory cells thandepicted in FIGS. 2A and 2B. For example, a wordline can includethousand or tens of thousands of memory cells. The discussion herein isnot limited to any particular number of memory cells in a wordline.

Each storage element can store data. For example, when storing one bitof digital data, the range of possible threshold voltages (V_(TH)) ofthe storage element is divided into two ranges which are assignedlogical data “1” and “0.” In one example of a NAND type flash memory,the V_(TH) is negative after the storage element is erased, and definedas logic “1.” The V_(TH) after a program operation is positive anddefined as logic “0.” When the V_(TH) is negative and a read isattempted, the storage element will turn on to indicate logic “1” isbeing stored. When the V_(TH) is positive and a read operation isattempted, the storage element will not turn on, which indicates thatlogic “0” is stored. A storage element can also store multiple levels ofinformation, for example, multiple bits of digital data. In this case,the range of V_(TH) value is divided into the number of levels of data.For example, if four levels of information are stored, there will befour V_(TH) ranges assigned to the data values “11”, “10”, “01”, and“00.” In one example of a NAND type memory, the V_(TH) after an eraseoperation is negative and defined as “11”. Positive V_(TH) values areused for the states of “10”, “01”, and “00.” The specific relationshipbetween the data programmed into the storage element and the thresholdvoltage ranges of the storage element depends upon the data encodingscheme adopted for the storage elements.

When programming a flash storage element, a program voltage is appliedto the control gate of the storage element, and the bit line associatedwith the storage element is grounded. Electrons from the channel areinjected into the floating gate. When electrons accumulate in thefloating gate, the floating gate becomes negatively charged and theV_(TH) of the storage element is raised. To apply the program voltage tothe control gate of the storage element being programmed, that programvoltage is applied on the appropriate word line. As discussed above, onestorage element in each of the NAND strings share the same word line.For example, when programming storage element 324 of FIG. 2A, theprogram voltage will also be applied to the control gates of storageelements 244 and 254.

FIG. 3 depicts a cross-sectional view of a NAND string formed on asubstrate. The view is simplified and not to scale. The NAND string 300includes a source-side select gate 306, a drain-side select gate 324,and eight storage elements 308, 310, 312, 314, 316, 318, 320 and 322,formed on a substrate 340. A number of source/drain regions, one exampleof which is source/drain region 330, are provided on either side of eachstorage element and the select gates 306 and 324.

In one approach, the substrate 340 employs a triple-well technologywhich includes a p-well region 332 within an n-well region 334, which inturn is within a p-type substrate region 336. The NAND string and itsnon-volatile storage elements can be formed, at least in part, on thep-well region. A source supply line 304 with a potential of V_(SOURCE)is provided in addition to a bit line 326 with a potential of V_(BL).Voltages, such as body bias voltages, can also be applied to the p-wellregion 332 via a terminal 302 and/or to the n-well region 334 via aterminal 303. During a read or verify operation, a control gate voltageV_(CGRV) is provided on a selected word line, in this example, WL4,which is associated with storage element 316. Further, recall that thecontrol gate of a storage element may be provided as a portion of theword line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6 and WL7 canextend via the control gates of storage elements 308, 310, 312, 314,316, 318, 320 and 322, respectively. A pass voltage, V_(READ) is appliedto the remaining word lines associated with NAND string 300. V_(SGS) andV_(SGD) are applied to the select gates 306 and 324, respectively.

FIG. 4 illustrates a non-volatile storage device 410 that may includeone or more memory die or chips 412. Memory die 412 includes an array(two-dimensional or three dimensional) of memory cells 400, controlcircuitry 420, and read/write circuits 430A and 430B. In one embodiment,access to the memory array 400 by the various peripheral circuits isimplemented in a symmetric fashion, on opposite sides of the array, sothat the densities of access lines and circuitry on each side arereduced by half. The read/write circuits 430A and 430B include multiplesense blocks 300 which allow a page of memory cells to be read orprogrammed in parallel. The memory array 400 is addressable by wordlines via row decoders 440A and 440B and by bit lines via columndecoders 442A and 442B. In a typical embodiment, a controller 444 isincluded in the same memory device 410 (e.g., a removable storage cardor package) as the one or more memory die 412. Commands and data aretransferred between the host and controller 444 via lines 432 andbetween the controller and the one or more memory die 412 via lines 434.One implementation can include multiple chips 412.

Control circuitry 420 cooperates with the read/write circuits 430A and430B to perform memory operations on the memory array 400. The controlcircuitry 420 includes a state machine 422, an on-chip address decoder424 and a power control module 426. The state machine 422 provideschip-level control of memory operations. The on-chip address decoder 424provides an address interface to convert between the address that isused by the host or a memory controller to the hardware address used bythe decoders 440A, 440B, 442A, and 442B. The power control module 426controls the power and voltages supplied to the word lines and bit linesduring memory operations. In one embodiment, power control module 426includes one or more charge pumps that can create voltages larger thanthe supply voltage.

In one embodiment, one or any combination of control circuitry 420,power control circuit 426, decoder circuit 424, state machine circuit422, decoder circuit 442A, decoder circuit 442B, decoder circuit 440A,decoder circuit 440B, read/write circuits 430A, read/write circuits430B, and/or controller 444 can be referred to as one or more managingcircuits.

FIG. 5 depicts an exemplary structure of memory cell array 400. In oneembodiment, the array of memory cells is divided into M blocks of memorycells. As is common for flash EEPROM systems, the block is the unit oferase. That is, each block contains the minimum number of memory cellsthat are erased together. Each block is typically divided into a numberof pages. A page is a unit of programming. One or more pages of data aretypically stored in one row of memory cells. A page can store one ormore sectors. A sector includes user data and overhead data. Overheaddata typically includes parity bits of an Error Correction Code (ECC)that have been calculated from the user data of the sector. A portion ofthe controller (described below) calculates the ECC parity when data isbeing programmed into the array, and also checks it when data is beingread from the array. Alternatively, the ECCs and/or other overhead dataare stored in different pages, or even different blocks, than the userdata to which they pertain. A sector of user data is typically 512bytes, corresponding to the size of a sector in magnetic disk drives. Alarge number of pages form a block, anywhere from 8 pages, for example,up to 32, 64, 128 or more pages. Different sized blocks and arrangementscan also be used.

In another embodiment, the bit lines are divided into odd bit lines andeven bit lines. In an odd/even bit line architecture, memory cells alonga common word line and connected to the odd bit lines are programmed atone time, while memory cells along a common word line and connected toeven bit lines are programmed at another time.

FIG. 5 also shows more details of block i of memory array 400. Block iincludes X+1 bit lines and X+1 NAND strings. Block i also includes 64data word lines (WL0-WL63), 2 dummy word lines (WL_d0 and WL_d1), adrain side select line (SGD) and a source side select line (SGS). Oneterminal of each NAND string is connected to a corresponding bit linevia a drain select gate (connected to select line SGD), and anotherterminal is connected to the source line via a source select gate(connected to select line SGS). Because there are sixty four data wordlines and two dummy word lines, each NAND string includes sixty fourdata memory cells and two dummy memory cells. In other embodiments, theNAND strings can have more or fewer than 64 data memory cells and moreor fewer dummy memory cells. Data memory cells can store user or systemdata. Dummy memory cells are typically not used to store user or systemdata. Some embodiments do not include dummy memory cells.

FIG. 6 is a block diagram of an individual sense block 300 partitionedinto a core portion, referred to as a sense module 480, and a commonportion 490. In one embodiment, there will be a separate sense module480 for each bit line and one common portion 490 for a set of multiplesense modules 480. In one example, a sense block will include one commonportion 490 and eight sense modules 480. Each of the sense modules in agroup will communicate with the associated common portion via a data bus472. For further details, refer to U.S. Patent Application Publication2006/0140007, filed Dec. 29, 2004, and titled, “Non-volatile memory andmethod with shared processing for an aggregate of read/write circuits,”which is hereby incorporated herein by reference in its entirety.

Sense module 480 comprises sense circuitry 470 that determines whether aconduction current in a connected bit line is above or below apredetermined threshold level. In some embodiments, sense module 480includes a circuit commonly referred to as a sense amplifier. Sensemodule 480 also includes a bit line latch 482 that is used to set avoltage condition on the connected bit line. For example, apredetermined state latched in bit line latch 482 will result in theconnected bit line being pulled to a state designating program inhibit(e.g., Vdd).

Common portion 490 comprises a processor 492, a set of data latches 494and an I/O Interface 496 coupled between the set of data latches 494 anddata bus 471. Processor 492 performs computations. For example, one ofits functions is to determine the data stored in the sensed memory celland store the determined data in the set of data latches. The set ofdata latches 494 is used to store data bits determined by processor 492during a read operation. It is also used to store data bits importedfrom the data bus 471 during a program operation. The imported data bitsrepresent write data meant to be programmed into the memory. I/Ointerface 496 provides an interface between data latches 494 and thedata bus 471.

During read or sensing, the operation of the system is under the controlof state machine 222 that controls the supply of different control gatevoltages to the addressed cell. As it steps through the variouspredefined control gate voltages corresponding to the various memorystates supported by the memory, the sense module 480 may trip at one ofthese voltages and an output will be provided from sense module 480 toprocessor 492 via bus 472. At that point, processor 492 determines theresultant memory state by consideration of the tripping event(s) of thesense module and the information about the applied control gate voltagefrom the state machine via input lines 493. It then computes a binaryencoding for the memory state and stores the resultant data bits intodata latches 494. In another embodiment of the core portion, bit linelatch 482 serves double duty, both as a latch for latching the output ofthe sense module 480 and also as a bit line latch as described above.

It is anticipated that some implementations will include multipleprocessors 492. In one embodiment, each processor 492 will include anoutput line (not depicted in FIG. 6) such that each of the output linesis wired-OR'd together. In some embodiments, the output lines areinverted prior to being connected to the wired-OR line. Thisconfiguration enables a quick determination during the programverification process of when the programming process has completedbecause the state machine receiving the wired-OR line can determine whenall bits being programmed have reached the desired level. For example,when each bit has reached its desired level, a logic zero for that bitwill be sent to the wired-OR line (or a data one is inverted). When allbits output a data 0 (or a data one inverted), then the state machineknows to terminate the programming process. In embodiments where eachprocessor communicates with eight sense modules, the state machine may(in some embodiments) need to read the wired-OR line eight times, orlogic is added to processor 492 to accumulate the results of theassociated bit lines such that the state machine need only read thewired-OR line one time.

During program or verify, the data to be programmed is stored in the setof data latches 494 from the data bus 471. The program operation, underthe control of the state machine, comprises a series of programmingvoltage pulses (with increasing magnitudes) applied to the control gatesof the addressed memory cells. Each programming pulse may be followed bya verify process to determine if the memory cell has been programmed tothe desired state. Processor 492 monitors the verified memory staterelative to the desired memory state. When the two are in agreement,processor 492 may set the bit line latch 482 so as to cause the bit lineto be pulled to a state designating program inhibit. This inhibits thecell coupled to the bit line from further programming even if it issubjected to programming pulses on its control gate. In otherembodiments the processor initially loads the bit line latch 482 and thesense circuitry sets it to an inhibit value during the verify process.

Data latch stack 494 contains a stack of data latches corresponding tothe sense module. In one embodiment, there are 3-5 (or another number)data latches per sense module 480. In one embodiment, the latches areeach one bit. In some implementations (but not required), the datalatches are implemented as a shift register so that the parallel datastored therein is converted to serial data for data bus 471, and viceversa. In one embodiment, all the data latches corresponding to theread/write block of m memory cells can be linked together to form ablock shift register so that a block of data can be input or output byserial transfer. In particular, the bank of read/write modules isadapted so that each of its set of data latches will shift data in to orout of the data bus in sequence as if they are part of a shift registerfor the entire read/write block.

Additional information about the read operations and sense amplifierscan be found in (1) U.S. Pat. No. 7,196,931, “Non-Volatile Memory AndMethod With Reduced Source Line Bias Errors,”; (2) U.S. Pat. No.7,023,736, “Non-Volatile Memory And Method with Improved Sensing,”; (3)U.S. Patent Application Pub. No. 2005/0169082; (4) U.S. Pat. No.7,196,928, “Compensating for Coupling During Read Operations ofNon-Volatile Memory,” and (5) United States Patent Application Pub. No.2006/0158947, “Reference Sense Amplifier For Non-Volatile Memory,”published on Jul. 20, 2006. All five of the immediately above-listedpatent documents are incorporated herein by reference in their entirety.

At the end of a successful programming process (with verification), thethreshold voltages of the memory cells should be within one or moredistributions of threshold voltages for programmed memory cells orwithin a distribution of threshold voltages for erased memory cells, asappropriate. FIG. 7 depicts example threshold voltage distributions forstates of memory cells in which there are eight states. The eight datastates include an erase state and states A-G. In this example, threebits may be stored per memory cell. Between each of the data states areread reference voltages used for reading data from memory cells. Forexample, FIG. 7 shows read reference voltage Vra between data stateserase and A, and Vrb between data states A and B. By testing whether thethreshold voltage of a given memory cell is above or below therespective read reference voltages, the system can determine what statethe memory cell is in. At or near the lower edge of each data state areverify reference voltages. For example, FIG. 7 shows VvA for state A andVvB for state B, etc. When programming memory cells to a given state,the system will test whether those memory cells have a threshold voltagegreater than or equal to the verify reference voltage.

Example Structures

FIG. 8A depicts one embodiment of non-volatile storage elements andtransistors. FIG. 8A is a view along a portion of a NAND string.Portions of two non-volatile storage elements on a NAND string and aselect gate of that NAND string may be seen. FIG. 8A also shows atransistor in a peripheral region. FIG. 8A omits elements that arebetween the NAND string and the peripheral transistor. Note that theview along the NAND string corresponds to a portion of line A-A′ of FIG.2B. FIG. 8B is a view along line B-B′ from FIG. 8A. FIG. 8B showsseveral non-volatile storage elements on adjacent NAND strings. FIG. 8Cis a view along line C-C′ from FIG. 8A. FIG. 8C shows several selectgate transistors on adjacent NAND strings.

In FIGS. 8A and 8B, the non-volatile storage elements have a floatinggate (FG) 811 with a P− semiconductor region 804 and a metal region 808.The p− region 804 resides over a tunnel oxide 805 a.

Each non-volatile storage element has a control gate 812 and aninter-gate dielectric 810 between the floating gate 811 and control gate812. The control gate 812 may be formed from doped polysilicon, frommetal, or a combination thereof.

Referring now to FIG. 8A, the substrate 340 has source/drain regions(S/D), which connect the non-volatile storage elements to form a NANDstring. Channel region 807 exists in the substrate 340 between thesource/drain regions. Thus, channel region 807 is below the floatinggate 811. More precisely, the channel region 807 is below the portion ofthe tunnel oxide 805 that is below the p− region 804 of the floatinggate 811. Note that having the p− region 804 near the channel 807 mayprovide for good data retention. Moreover, erase operation is notnecessarily harmed significantly by the p− region 804.

Referring now to FIG. 8B, the control gate 812 may wrap around the upperportion of the floating gate 811. For example, the control gate 812 maybe over the top and around at least a portion of the sides of thefloating gate 811. Thus, the metal region 808 is near the control gate812. Stated another way, the metal region 808 borders substantialportions of the inter-gate dielectric 810 that separate the control gate812 from the floating gate 811. It is not required that the metal region808 border every portion of the inter-gate dielectric 810 that separatesthe control gate 812 from the floating gate 811. Note that having themetal region 808 near the control gate 812 may lead to a good capacitivecoupling ratio between the control gate and floating gate duringprogramming and also during erase operation.

Still referring to FIG. 8B, shallow trench isolation (STI) structures836 in the substrate 340 electrically isolates NAND strings. Forexample, the STI structures 836 may provide electrical isolation betweensource/drain regions and channels 807 of adjacent NAND strings. In thisexample, the STI structures 836 extend part way up the sides of themetal regions 808. Note that the STI structures 836 might extend to adifferent height. For example, the STI structures 836 could extendhigher or lower than depicted in FIG. 8B. In this example, a portion ofthe inter-gate dielectric 810 resides over the STI structures 836.

Referring back to FIG. 8A, transistors will now be discussed. Thefollowing may apply both to the select gate transistor at the end ofNAND string and to the peripheral transistor. For purposes ofdiscussion, the transistor gate 813 includes several conductive regions(821 a, 821 b, 821 c). In this embodiment, the gate of a transistor hasa p− region 821 a, a metal region 821 b, and an upper-most region 821 c,which may be N+, P+, or metal.

Referring now to upper portions of the transistor gate 813, a smallamount of inter-gate dielectric 810 may remain in the transistor gate asa result of the fabrication process. However, the inter-gate dielectric810 is not required. Note that, in some embodiments, at least some ofthe inter-gate dielectric 810 is etched away in regions wheretransistors are formed.

Also note that the very upper portion 821 c of the transistor gate 813may be formed from material that was deposited to form the memory cellcontrol gates 812. In some embodiments, the control gates 812 are formedfrom N+ polysilicon. Therefore, the very upper portions 821 c oftransistor gates may be formed from N+ polysilicon. In some embodiments,the control gates 812 are formed from P+ polysilicon. Therefore, thevery upper portions 821 c of transistor gates may be formed from P+polysilicon. However, at least a portion of the control gates 812 mayalternatively be formed from metal. In this alternative, the very upperportion 821 c of the transistor gate may be formed from metal.

Finally, note that the gate oxide 805 b in the peripheral region may bethicker, the same thickness, or thinner than the tunnel oxide 805 a inthe memory array region. In some embodiments, the gate oxide 805 b isdifferent thicknesses in different regions of the periphery. This mayallow for regions of high-, medium, and low-voltage transistors, forexample.

FIG. 8C depicts four select gate transistors on different NAND strings.FIG. 8C is a view along line C-C′ of FIG. 8A. The gate of eachtransistor includes a lower region 821 a, N+ region 821 b, and veryupper region 821 c. These regions have already been discussed inconnection with the discussion of FIG. 8A. As noted, the lower region821 a are P− in this embodiment. As can be seen, the inter-gatedielectric 810 has been etched back such that region 821 c may have goodelectrical contact to metal region 821 b. Some of the inter-gatedielectric 810 may remain. Note that etching back the inter-gatedielectric 810 may reduce the height of the metal region 821 b relativeto the metal region 808 in the floating gates.

Note that although the p− region 804 may be desirable for lower portionsof the floating gate 811, it may not be desirable to have a p− region inthe gates of transistors. This may apply for both select gatetransistors, as well as transistors in the peripheral region of thememory array. However, note that the transistor gates may be formedusing similar materials used to form the floating gate stacks. Forexample, after initial deposition steps, the region in which transistorgates will be formed may be a p− region.

In one embodiment, the transistor gates are mostly (or all) polysilicon.For example, the transistor gates are mostly (or all) N+ polysilicon.Referring now to FIG. 8D, both the select gate and the peripheraltransistors are mostly N+ polysilicon. There may be some residualinter-gate dielectric 810. FIG. 8E depicts a view along line D-D′ fromFIG. 8D. FIG. 8E depicts several select transistors from adjacent NANDstrings. Techniques are disclosed below for forming transistors withouta p− region in the same process as forming memory cells having a p−region. Note that although the transistor gate is depicted as onecontinuous N+ region in FIGS. 8D-8E, the gate may be formed in severaldistinct steps. For example, a lower, middle and upper portion of thetransistor gate may be formed as a result of different deposition steps.

In one embodiment, the lower portion of transistor gates are N+ andupper portion is metal. FIG. 8F shows that the transistor gates have ametal region 821 e at the top and an N+ region 821 d at the bottom. Themiddle portion 821 b is also metal. The transistors may be fabricatedduring the same process as the memory cells. Note that region 821 e maybe formed from the same material used to form upper portions of thecontrol gates 812. Therefore, at least the upper portions of controlgates 812 may be metal, in this embodiment. Note that another option isfor the uppermost region 821 e to be doped polysilicon.

Note that the floating gates could have a different shape. FIG. 9Adepicts one embodiment in which the floating gates 811 have an invertedT-shape. FIG. 9A depicts two memory cells on adjacent NAND strings. Theview is along line B-B′ from FIG. 8A. Note that the view along the NANDstring for this embodiment could appear similar to the embodiment ofFIG. 8A.

In one embodiment, the transistor gates are N+ at the bottom and N+ inthe middle; however, floating gates are p− at the bottom and metal inthe top of the floating gate. Referring to the embodiment of FIG. 8G,the transistor gates 813 have n+ region 821 a, etch stop layer 819, N+region 821 f, and upper most region 821 g. The uppermost region 821 gcould be formed from a variety of materials including doped polysilicon(for example, N+) and metal. The etch stop layer 819 may be a thinbarrier (e.g., an insulator or dielectric that is a few Angstromsthick). This etch stop layer 819 may serve as an etch stop layer duringprocessing, while ensuring the n+ region 821 a and the N+ region 821 fare not electrically insulated from each other. The etch stop layer 819in the floating gates is of suitable material and thickness such that p−region 804 and the metal region 808 are not electrically insulated fromeach other.

Referring now to FIG. 9A, the floating gate 811 has a base (or lowerportion) and a stem (or upper portion). In this embodiment, the p−region 804 is in the base and the metal region 808 is in the stem. Thep− region 804 could extend into the stem, or the metal region 808 couldextend into the base.

In this example, the control gate 812 wraps around the upper portion ofthe floating gate. For example, the control gate 812 is over the top andaround at least a portion of the sides of the floating gate 811. Thus,the metal region 808 is near the control gate 812. Stated another way,the metal region 808 borders substantial portions of the inter-gatedielectric 810 that separate the control gate 812 from the floating gate811. It is not required that the metal region 808 border every portionof the inter-gate dielectric 810 that separates the control gate 812from the floating gate 811. Note that having the metal region 808 nearthe control gate 812 may lead to a good capacitive coupling ratiobetween the control gate and floating gate during programming and alsoduring erase.

Still referring to FIG. 9A, shallow trench isolation (STI) 836 in thesubstrate 340 electrically isolates NAND strings. For example, the STI836 may provide electrical isolation between source/drain regions andchannels 807 of adjacent NAND strings. In this example, the STI 836extends up to the base of the floating gate 811. Note that the STI 836might extend to a different height. For example, the STI 836 couldextend higher or lower than depicted in FIG. 8B. In this example, aportion of the inter-gate dielectric 810 resides over the STI 836.

One embodiment is what may be referred to as a “flat cell.” In thisembodiment, the control gate 812 does not wrap around sides of thefloating gate 811. FIG. 9B shows a perspective for one embodiment alongline B-B′ of FIG. 8A. As can be seen in FIG. 9B, the control gate 812does not wrap around the sides of the floating gate 811. In thisembodiment, the inter-gate dielectric 810 does not wrap around the sidesof the floating gate 811 either. The floating gate 811 has a P− region804 bordering the tunnel oxide 805 a, and a metal region 808 borderingthe inter-gate dielectric 810 between the floating gate 811 and controlgate 812. Referring back to FIG. 8A, the control gate 812 does not wraparound the floating gate 811 from this perspective either.

Example Band Diagrams

FIGS. 10A-13C depict energy band diagrams. FIGS. 10A-12C cover cases inwhich the floating gate is formed entirely from one conductivity. FIGS.13A-13C correspond to embodiments having a floating gate (FG) that has aP− region and a metal region. Note that the band diagrams in FIGS.10A-12C are useful for purposes of discussion of P−/metal floatinggates.

FIG. 10A is for an N+FG. FIG. 10B is for a P+FG. FIG. 10C is for a P−FG. FIGS. 10A-10C will be used to discuss data retention. Referring toFIG. 10A, five distinct regions are depicted from left to right. Theseregions correspond to a silicon channel, a tunnel oxide, an N+ floatinggate, an inter-gate dielectric, and a control gate. FIGS. 10B and 10Cdiagrams have a similar organization, but are for different floatinggate materials.

Conduction bands 1002 and valence bands 1004 for silicon regions areshown as solid lines. The Fermi levels 1006 are depicted as dashedlines. A charge loss barrier is depicted as the difference between theFermi level 1006 of the FG and the conduction band of the tunnel oxide.As can be seen, the P+FG of FIG. 10A offers higher barrier to electronsthan the N+FG of FIG. 10A, thus improving data retention. As one examplein which the channel is silicon and the tunnel oxide is SiO₂, theelectron barrier might be about 3.1 eV for an N+FG. However, for a P+FGthe electron barrier might be about 4.2 eV. For a P− FG, the electronbarrier could be about between about 3.65 eV and 4.2 eV, depending onthe P− concentration, at least for some materials. Note that for someembodiments, the tunnel oxide is thinner than the inter-gate dielectric.Under this scenario charge loss (e.g., data retention) could be agreater problem across the tunnel oxide than across the inter-gatedielectric.

As will be discussed below, having a P+ region in the FG near the tunneloxide may also make the barrier to remove electrons during erase largerthan having an N+ region in the FG near the tunnel oxide may. Therefore,a FG with such a P+ region may be harder to erase than a FG having an N+region near the tunnel oxide. FIGS. 11A-11C will be used to discusserase. FIG. 11A is for an N+FG. FIG. 11B is for a P+FG. FIG. 11C is fora P− FG. Each of these diagrams shows an erase voltage (VERA) applied tothe control gate. Also depicted is an erase barrier, which is thedifference between the Fermi level 1006 of the FG and the conductionband of the tunnel oxide. The erase barrier for the N+FG may be about3.1 eV. The erase barrier for the P+FG may be about 4.2 eV. The erasebarrier for the P− FG may be about 3.1V, at least for some P−concentrations. Note that with a different P− concentration, the erasebarrier may be different.

Note that for the P− FG, there may be some inversion at the tunnel oxideinterface. This inversion may help lower the erase barrier. For example,note that due to the inversion the erase barrier for P− FG may be lessthan the data retention barrier for P− FG. In contrast, for P+FG theerase barrier may be about the same as the data retention barrier forP+FG. Moreover, note that the erase barrier of the P− FG comparesfavorably to the erase barrier for the P+FG. That is, during eraseoperation, it may be desirable to have a low barrier to electrons forefficient erase operation.

FIGS. 12A-12C are band diagrams illustrating programming characteristicsof N+FG, P+FG, and P− FG, respectively. A program voltage, VPGM, isapplied to the control gate. For N+FG of FIG. 12A, poly-depletion mayoccur during programming in the FG close to tunnel oxide interface.

For P+ or for P− FG of FIGS. 12B and 12C, poly-depletion may occur inthe FG close to inter-gate dielectric interface, which may result inlower coupling ratio. However, having a metal region near the inter-gatedielectric may improve the coupling ratio relative to either a P+ or P−region. Therefore, a FG having metal near the inter-gate dielectric mayprogram more efficiently than a FG having a P-type semiconductor nearthe inter-gate dielectric.

In one embodiment, the FG is P− near the tunnel oxide and metal near thecontrol gate. This may achieve good data retention, efficient erase, andefficient programming. A P− region bordering the tunnel oxide may havebetter data retention than N+FG due to increased electron barrier at thetunnel oxide interface. Erase operation for a FG having a p− region nearthe tunnel oxide may be efficient due to inversion at the p− doped FG atthe tunnel oxide interface. For example, the erase operation may be moreefficient than a FG having a p+ region near the tunnel oxide. Thecoupling ratio during programming of a FG having a metal region near thecontrol gate (e.g., bordering the inter-gate dielectric) may be betterthan a FG with a P-type semiconductor near the control gate. Thecoupling ratio during erase of a FG having a metal region near thecontrol gate (e.g., bordering the inter-gate dielectric) may be betterthan a FG with an N-type semiconductor near the control gate.

FIGS. 13A-13B are band diagrams illustrating programming and erasecharacteristics of memory cell having a FG that has a p− regionbordering the tunnel oxide and a metal region bordering the inter-gatedielectric.

FIG. 13A depicts a band diagram under programming for one embodiment. Ascan be seen, there is no polysilicon depletion at either the tunneloxide interface or the inter-gate dielectric interface. Therefore, thecoupling ratio between the control gate and floating gate may be good.Consequently, an embodiment having a P−/metal floating gate programsefficiently. Moreover, with a high work-function metal, there may beless program saturation due to an increase in the barrier height at theinter-gate dielectric.

FIG. 13B depicts a band diagram under erase for one embodiment. There isinversion at the FG to tunnel oxide interface, due to the FG being P− atthis interface. Therefore, the electron barrier during erase may bebetter (e.g., less) than P+FG and comparable to N+FG. Moreover, due tometal at inter-gate dielectric interface, there is no poly-depletion atthis interface unlike N+FG. Consequently, an embodiment having aP−/Metal floating gate erases efficiently.

FIG. 13C depicts a band diagram for one embodiment to demonstrateimprovements in data retention. There may be improvements for the boththe tunnel oxide side and the inter-gate dielectric side of the floatinggate. Because the FG is P− near the tunnel oxide, data retention may bebetter than if the FG is N+ near the tunnel oxide. Moreover, dataretention may be almost as good as the case in which the FG is P+ nearthe tunnel oxide. Stated another way, the charge loss barrier at the FGto tunnel oxide interface may be relatively large. Also, the charge lossbarrier at the metal FG to inter-gate dielectric may be relatively largecompared to floating gates of other materials. For example, referringback to FIG. 10A, the charge loss barrier at the IPD interface isrelatively low for an N+FG. Therefore, embodiments having a P−/metal FGhave good data retention at both interfaces of the FG.

Process Flows

As mentioned, embodiments include a P−/metal type of FG. Since the metalpart of floating gate may susceptible to high temperature process, postmetal floating gate formation processing may have low temperaturelatitude to control metal reaction and diffusion. For example, employinglow temperature chemical vapor deposition (CVD) oxide process may bepreferred to high temperature oxide (HTO) process. Also, the sameprocess may be applied to the interface between the metal part of the FGand the inter-gate dielectric. Regarding the control gate, either asilicide control gate (N+ or P+ poly control gate) or metal gate can beapplicable to this process. Furthermore, deposition of various materials(e.g., polysilicon for the control gates and inter-gate dielectric) isperformed using a low thermal budget process, in some embodiments.

Several different process flows for P−Metal hybrid type floating gateare disclosed herein. In one embodiment, the process concludes with thetransistors having a lower p− region (near the gate oxide). As notedherein, having a p− region near the gate may impact the thresholdvoltage. Thus, in other embodiments, the process concludes with thetransistors not having a p− region. Thus, the threshold voltage oftransistors may be tuned based on the process used. If desired, methodssuch as gate replacement technique to replace the “P−Metal” CMOS gatesby “N+Metal” gates may be used.

FIG. 14 is a flowchart of one embodiment of a process 1400 of forming amemory array with memory cells having P−/metal floating gates andtransistors having P−/metal gates. Process 1400 may be used to form anyof the memory cells and transistors shown and described in FIGS. 8A-9B,as well as other memory cells and transistors not specifically shown ordescribed. Note that the steps are described in process 1400 in acertain sequence as a matter of convenience. The steps may occur in adifferent order.

In step 1402, transistors are formed. These may be formed in the memoryarray region (e.g., select transistors) or in a peripheral region. Anindividual transistor may include a gate 813 and a gate oxide 805 b.

In step 1404, non-volatile storage elements are formed. Step 1404 mayinclude several sub-steps. Sub-steps 1404 a-1404 d for forming a givenstorage element may be as follows. In step 1404 a, a tunnel oxide 805 ais formed over a region for a channel 807 in a substrate 340. In step1404 b, a floating gate 811 is formed over the tunnel oxide 805 a. Thefloating gate 811 has a first region 804 formed from P− semiconductorand a second region 808 formed from metal. The first region 804 bordersthe tunnel oxide 804 over the channel region 807. In step 1404 c, aninter-gate dielectric 810 is formed. The inter-gate dielectric 810borders the metal region 808 of the floating gate 811. In step 1404 d, acontrol gate 812 is formed. Note that the inter-gate dielectric 810separates the floating gate 811 and the control gate 812.

Note that the doping concentration in the P− semiconductor region may bechosen to achieve a desired balance of various performancecharacteristics such as data retention and erase efficiency. A weakp-type doping level may provide better erase efficiency than a heavyp-type doping. However, data retention may improve when p-type doping isheavier. A suitable level of p-type doping may be selected to achievedesired erase efficiency, while also providing desired data retention.In one embodiment, the level of p-type doping is selected such that, atleast during erase operation, there will be some inversion near theFG-to-tunnel oxide interface, which lowers the energy barrier such thatelectrons may cross the tunnel oxide more easily.

FIG. 15A is a flowchart one embodiment of a process 1450 of formingtransistors and non-volatile storage elements. Process 1450 is oneembodiment of steps 1402 and 1404 from process 1400. In process 1450,the transistors are p− semiconductor near the gate oxide and metal awayfrom the gate oxide. Process 1450 may be used to form non-volatilestorage elements and transistors such as those depicted in FIGS. 8A-8Cand 9A-9B, a well as others not specifically shown or described herein.

In step 1452, a P− semiconductor region is formed over an insulator inone or more first regions in which the non-volatile storage elements andin one or more second regions in which the transistors are to be formed.The P− semiconductor region will serve as a p-region 804 for floatinggates and as a p-region 821 a for transistor gates.

In step 1454, a metal region is formed over the P− semiconductor regionin the one or more first regions and in the one or more second regions.The metal region will serve as a metal region 808 for floating gates andas a metal region 821 b for transistor gates.

In step 1456, the floating gates for the non-volatile storage elementsare formed in the one or more first regions from the P− semiconductorregion and the metal region that remains in the one or more firstregions. The insulator that was formed in step 1452 serves as the tunneloxide 805 a in a memory array region.

In step 1458, the transistor gates are formed in the one or more secondregions. The transistor gates include at least the metal 821 b and theP− semiconductor region 821 a. The insulator that was formed in step1452 serves as the gate oxide 805 b in a peripheral region. Note thatthe transistor gates could also have an uppermost portion 821 a formedfrom material used to form control gates of memory cells.

FIG. 15B depicts one embodiment of a process 1500 for formingnon-volatile storage elements and transistors. Process 1500 showsfurther details of one embodiment of process 1450 of FIG. 15A. FIG. 15Bwill be discussed with respect to FIGS. 16A-16E, which show resultsafter various steps of process 1500. Note that the flowchart does notdescribe all implant steps, the gap fill of etched volumes between thefloating gate stacks, or forming the contacts, metallizations, vias, andpassivation, as well as other portions of the manufacturing processknown in the art. There are many ways to manufacture memory according toembodiments and, thus, the inventors contemplate that various methodsother than that described by FIG. 15B can be used. While a flash memorychip will include core memory and peripheral circuitry, the processsteps of FIG. 15B are intended only to describe in general terms onepossible process for the fabrication of portions of a memory array. Forexample, the floating gates can be formed to have many different shapes.In some embodiments, the floating gates have a relatively wide base witha relatively narrow stem above the base.

Step 1502 includes growing oxide material on top of a silicon substrate.The substrate may be etched in preparation for growing the tunnel oxide.The substrate may be etched to different levels, based on the thicknessof tunnel oxide that is desired. Then, a tunnel (or gate) oxide layermay be grown over the substrate in both the memory array and peripheralregion. Nitridation may be performed to improve gate oxide quality.

In step 1504, a p-type semiconductor is formed over the oxide layer. Forexample, a polysilicon layer that will be used to form the floatinggates is deposited over the oxide material using CVD, PVD, ALD oranother suitable method. Thus, the semiconductor may be silicon. Thislayer may be doped as deposited or doped after depositing. In oneembodiment, this layer is a p− (also referred to as a weakly dopedp-layer). As one example, the doping concentration may be 1.0×10¹⁹/cm³.However, the doping concentration could be lower or higher. An exampleimpurity is boron.

In step 1506, a metal region may be formed over the p-typesemiconductor. This layer may be for upper portions of floating gates,as well as for portions of transistor gates. FIG. 16A shows resultsafter step 1506. FIG. 16A shows various layers in a region in whichmemory cells on several NAND strings are being formed and a region inwhich a peripheral transistor is being formed. The view may be along theline B-B′ in FIG. 8A. FIG. 16A shows the results after initial steps toform a structure similar to the one of FIG. 8B, with a peripheraltransistor also being formed. There is an oxide layer 1605 a, 1605 bover a substrate 340. Note that the oxide layer 1605 b may be thicker incertain regions for the peripheral transistor (such as high voltagetransistors), than the layer 1605 a in the memory array (e.g., NANDstring) region. Parts of the P− region 1604 will eventually become lowerparts of floating gates, as well as lower parts of transistor gates.Metal region 1608 will be used for upper portions of floating gates, aswell as a portion of transistor gates.

In step 1508, a SiN hard mask is formed over the metal region 1608 toallow etching to form STI structures. Forming the SiN mask may beperformed as follows. First, SiN may be deposited over the entire metalregion 1608 using, for example, CVD. Next, a photoresist layer may beadded over the SiN. The photoresist may be exposed and developed to forma mask pattern. The pattern may be transferred to the SiN, thus formingthe SiN hard mask.

In step 1510, shallow trench isolation trenches are formed based on theSiN hard mask. In step 1512, the metal region 1608, the p− polysiliconlayer 1604, the tunnel oxide material 1605, and the top of the siliconsubstrate 340 may be etched. This may be achieved with reactive ionetching (RIE). In one embodiment, the etch is approximately 0.2 micronsinto the substrate 340 to create shallow trench isolation (STI) areas,where the bottom of the trenches are inside the top of the P-well.Forming the shallow trench isolation trenches also etches thepolysilicon into strips that run in the direction of what will becomeNAND strings. Thus, the STI structures will separate adjacent NANDstrings. After the etch, cleaning is done (e.g., a STI wet clean isperformed).

Note that the etching to form STI trenches may cause some damage to thep-polysilicon 1604. In one embodiment, a step 1512 of selectiveoxidation (FG/AA) may be performed to remove damage that the etch mayhave caused to the polysilicon. However, it is desirable to not oxidizethe metal 1608. Thus, this may be a selective oxidation (FG/AA). In step1514, the structure may be encapsulated with, for example, SiO₂ toprevent further process damage. This may cover sidewalls of the metaland p− polysilicon.

In step 1516, the STI trenches are filled with isolation material suchas TEOS (Tetraethyl orthosilicate), HDP (High Density Plasma),Polysilazane (PSZ), SiO₂ (or another suitable material) up to the top ofthe SiN hard mask using CVD, rapid ALD or another method. In step 1518,chemical mechanical polishing (CMP), or another suitable process, isused to polish the isolation material flat until reaching the SiN hardmask.

FIG. 16B depicts results after step 1518. FIG. 16B is the sameorientation as FIG. 16A. FIG. 16B depicts STI structures 836 separatingwhat will become memory cells on different NAND strings. Note that thefloating gates are not yet completely formed. Later steps of process1500 will discuss completing formation of the floating gates. Thus, themetal portions 1608′ will eventually become metal regions 808 infloating gates. Oxide portions 1605 a′ will be used for the tunnel oxide805 a. The SiO₂ 1609 may be seen on the sidewalls of the substrate 340,the p-polysilicon 1604′, and metal 1608′. As discussed, the SiO₂ 1609may protect the metal 1608′. The SiN hard mask 1607 may be seen yet inplace.

Step 1520 is etching back the STI isolation material. Step 1522 isremoving the SiN hard mask. In step 1524, the inter-gate dielectric isgrown or deposited. The inter-gate dielectric may include alternatingconformal layers of oxide and nitride. For example, an Oxide NitrideOxide (ONO) inter-poly dielectric is used. In one embodiment, theinter-gate dielectric comprises nitride-oxide-nitride-oxide-nitride.

In step 1526, a first layer of polysilicon (or another semiconductor) isformed for lower portions of control gates of memory cells (note thatthis may also used for transistor gates). In some embodiments, this isN+ semiconductor (either as deposited, or doped later).

In step 1528, etching is performed in transistor regions to form a“cuttout”. This cuttout cuts through at least some of the inter-gatedielectric in the transistor regions. A control gate/IPD cutout is madein regions in which control gates of transistors (e.g., select gatetransistors) will be formed. The cutouts may also be formed in regionswhere control gates of periphery transistors will be formed. A reasonfor these cutouts is to form control gates that do not have the IPDforming a barrier. In other words, whereas memory cells have a floatinggate that is separated from the control gate by the IPD, gates oftransistors should not have a floating gate. Therefore, a portion of theIPD is removed where select gates and other transistors will be formed.FIGS. 16C-16D depict results after step 1528. FIG. 16C depicts resultsalong the view similar to FIGS. 16A-16B. FIG. 16C shows a conformallayer of inter-gate dielectric 810 over the metal 1608′ in the NANDstring region. Over that is a polysilicon region 1612, which may be usedfor lower parts of control gates. Region 1612 may be N+ semiconductor.Note that a “cuttout” has been made at least through the inter-gatedielectric 810 where the peripheral transistor is being formed. It isacceptable for some inter-gate dielectric to remain in the transistorgate region. However, all of the inter-gate dielectric may be removed inthe transistor gate region.

FIG. 16D shows initial formation of a part of a NAND string, but doesnot depict formation of a peripheral transistor. However, note that theNAND string has a select transistor at the end. FIG. 16D shows resultsalong the view similar to FIG. 8A. FIG. 16D shows various layers ofmaterials that have already been discussed. Note that from this view,the inter-gate dielectric 810 is a relatively flat layer, although thisis not a requirement. A “cuttout” has been made at least through theinter-gate dielectric 810 in preparation for forming the gate of theselect transistor. It is acceptable for some inter-gate dielectric 810to remain in the transistor gate region. However, all of the inter-gatedielectric 810 may be removed in the transistor gate region. Note thatin this embodiment, the etching of the cuttout does not etch into themetal region 1608′. In another embodiment, the etching of the cuttoutmay etch into the metal region 1608′.

In step 1532, a second layer of polysilicon (or another material) isformed for the control gates of memory cells (note that this is alsoused for transistor gates). In some embodiments, this is N-type (eitheras deposited, or doped later). In one embodiment, metal is formedinstead of depositing a semiconductor in this step. Thus, the upperportions of control gates may be metal.

In step 1534, a mask layer may be formed over the second layer ofpolysilicon. A pattern is formed in the mask such that etching can laterbe performed to create floating gate stacks and control gates ortransistors. In one embodiment, a SiN hard mask is patterned as follows.SiN may be deposited over the entire third layer of polysilicon using,for example, CVD. A photoresist layer may be added over the SiN. Thephotoresist may be exposed and developed to form a mask pattern. Thepattern is transferred to the SiN, thus forming the SiN hard mask.Floating gate stacks and transistor stacks may be formed by etchingbased on the mask, in step 1536.

After etching, a sidewall (SW) ULT SiO₂ may be performed in step 1538 toprevent damage to the metal (and polysilicon). This may be a lowtemperature deposition (e.g., 300-500 C). The SiO₂ may be about 2 nm-10nm, as examples. However, the SiO₂ could be thinner or thicker.

In step 1540, doping may be performed to create source/drain regions formemory cells, as well as a source and/or drain regions for transistors(e.g., select gate transistor, periphery transistors). The hard mask mayremain in place while doping to create the source/drain regions. Laterthe hard mask may be removed. In step 1542, a thermal anneal isperformed. This thermal anneal serves to diffuses the dopants that wereimplanted during step 1540. Note that other structures, such asresistors may be formed during the same process flow.

FIG. 16E depicts results after step 1540. FIG. 16E shows the view alongthe NAND string. Note that the diagram is not necessarily to scale. Forexample, source/drain regions of the transistors might be wider than forthe memory cells. Likewise, the transistor gate might be wider than thewidth of floating gate stacks. Note that the SiO₂ that was added usingULT in step 1538 may be seen as layer 899 along the sidewalls of thefloating gate stacks and the select gate stack. Transistor stacks in theperipheral region (not depicted in FIG. 16E) may also have a layer ofSiO₂ on their sidewalls as a result of step 1538. Note that someresidual inter-gate dielectric 810 and some residual of N+ layer 1612are shown in the transistor gate. These are not required elements.

FIG. 17A depicts one embodiment of a process 1700 for formingnon-volatile storage elements and transistors. Process 1700 is oneembodiment of steps 1402 and 1404 from process 1400. In process 1700,metal that is initially deposited where transistors are being formed isremoved, such that the transistors are N+ semiconductor. Process 1700may be used to form non-volatile storage elements and transistors suchas those depicted in FIG. 8D, as well as others not specifically shownor described herein.

Steps 1502-1526 are similar to process 1500. Included in these steps areforming a P− semiconductor region over an insulator in one or more firstregions in which the non-volatile storage elements and in one or moresecond regions in which the transistors are to be formed. Moreover, ametal region is formed over the P− semiconductor region in the one ormore first regions and in the one or more second regions. Further, aninter-gate dielectric is formed.

In step 1702, the inter-gate dielectric and the metal are etched in theregions where transistors are to be formed. Note that this etch may goall the way down to the p− polysilicon.

In step 1704, counter-doping is performed to change the p-polysilicon ton+ polysilicon in regions where transistor gates are to be formed. FIGS.18A and 18B shows results of step 1704. FIGS. 18A-18B are similar inperspective to FIGS. 16C and 16D, respectively. FIG. 18A shows severalmemory cells being formed on different NAND strings and a transistorbeing formed in a peripheral region. FIG. 18B depicts a view along aNAND string. The cuttout region (with arrows) depicts a region in whicha select gate transistor is being formed. The arrows represent thecounter-doping. The portion of the transistor gate that is near the gateoxide 1605′ has been changed to an N+ type region 1804.

After counter-doping, a semiconductor, such as silicon, may be depositedin step 1706. This silicon may be doped N+. Note that silicon may beformed in the etched away portions of the metal where the transistorgates are to be formed. Then, processing may be similar to steps1534-1542 of process 1500. Results may be as depicted in FIG. 8D. Inthis example, most of the transistor gate is N+. Note that depending onhow the cuttout was formed, there may not be any residual inter-gatedielectric in the transistor gates. However, note that if there is someresidual intergate dielectric 810, there may also be some residual metaljust below the dielectric 810. That is, the etching of the metal in step1702 might not remove all of the metal below the residual intergatedielectric 810.

In another embodiment, after the step of counter-doping (e.g., afterstep 1704 of FIG. 17A), rather than filling the etched away portions ofthe metal with polysilicon, metal is used to fill the etched awayportions of the metal where transistor gates are to be formed. FIG. 17Bdepicts one embodiment of a process 1720 for forming memory array inaccordance with this embodiment. Process 1720 is similar to process1700, but has step 1726 of depositing metal rather than depositingsilicon. Note that this metal may also be used for at least a portion ofthe control gates of memory cells. Results may be as depicted in FIG.8F. Note that the transistor gate is N+ 821 d at the very bottom. Asnoted above, this N+ region 821 d may have been formed by counter-dopingthe p− region that was used for the floating gates. However, the rest ofthe transistor gate may be metal.

FIG. 19 is a flowchart of one embodiment of a process 1800 of formingtransistors and non-volatile storage elements. Process 1800 is oneembodiment of steps 1402 and 1404 from process 1400. In process 1800,the transistors may be N+ semiconductor near the gate oxide, as well asN+ away from the gate oxide. Process 1800 may be used to formnon-volatile storage elements and transistors such as those depicted inFIG. 8G, a well as others not specifically shown or described herein.Note that some steps may be similar to that of process 1500. Therefore,similar reference numerals are used.

After forming the n+ polysilicon layer (or first semiconductor region)in step 1504, an etch stop layer is formed over the n+ polysilicon instep 1805. Note that both the n+ polysilicon layer and the etch stoplayer may be formed in both the regions where memory cells are beingformed and the peripheral region. However, ultimately the etch stoplayer may only be needed where floating gates are being formed.

In step 1806, a region of N+ polysilicon (or second semiconductorregion) is formed over the etch stop layer. Note that this N+semiconductor is formed both in regions where floating gates and wheretransistor gates are to be formed. However, it will later be removed inthe regions where floating gates are to be formed. Results after step1806 are depicted in FIG. 20A, which shows initial formation in a memoryarray region and a peripheral region. The various layers include asubstrate 340, oxide 1605 a, 1605 b, N+ semiconductor 2004, etch stoplayer 2005, and n+ semiconductor 2008.

Next, steps 1508-1518 are performed. After step 1518, STI trenches havebeen formed and filled. Moreover, in step 1518 CMP may be used toplanarize the STI oxide. Then, in step 1813, the SiN hard mask that wasformed in step 1508 may be removed. Next, in step 1815, masking isperformed above the regions where select gate transistors are beingformed. Masking may also be performed in region where peripheraltransistors are being formed.

Then, in step 1817, the N+ polysilicon that was deposited in step 1806is removed from regions where the floating gates will be formed. Thus,trenches are formed where floating gates are to be formed. Note thatportions of the etch stop layer 2005′ that was formed in step 1805 maystill be in place. In step 1819, counter-doping is performed to convertthe n+ semiconductor to p− semiconductor where floating gates are beingformed. Note that the counter-doping may be performed through the etchstop layer. FIG. 20B depicts results after step 1819, showing thetrenches where floating gates are to be formed. Both n+ semiconductorregions 2004′, 2008′ still remain where transistor gates are to beformed. A mask 2035 is shown over the n+ semiconductor 2008′ where theperipheral transistors is being formed. However, the original n+semiconductor 2004 has been converted to p− semiconductor 2034 wherefloating gates are being formed. Note that the perspective of FIG. 20Bdoes not depict the select gate transistor being formed, but there maybe a mask over that region at this point in the process to prevent then+ semiconductor from being removed. Also note that the mask 2035 mayprevent the counter-doping from affecting the upper n+ semiconductor2008 in regions where transistor gates are being formed.

In step 1820, the trenches are filled with metal. In step 1821, the maskfor the transistors may be removed. In step 1822, CMP of the metal forthe floating gates is performed. Results are as depicted in FIG. 20C,which shows metal regions 2007 where floating gates are being formed.Then, the STI oxide may be etched back in step 1520. Next, steps1524-1542 may be performed to complete processing. Results may be asdepicted in FIG. 8G, which shows the etch stop 819 between the p−polysilicon 804 and the metal 808 of the floating gates. As noted, theetch stop 819 may not needed in the transistor gates. However, the etchstop 819 could be present in transistor gate stacks between the N+region 821 a and n+ region 821 f.

There are many alternatives to the above described structures andprocesses within the spirit of the present disclosure. As in theexisting NAND embodiments, an alternative is to fabricate the memorycells from PMOS devices with opposite polarity bias conditions for thevarious operations as compared to the existing NMOS implementation. Inthe above examples, the substrate is made of silicon. However, othermaterials known in the art can also be used such as Gallium Arsenide,etc.

One embodiment disclosed herein includes a non-volatile storage element,which may include: a channel region in a substrate, a tunnel oxide overthe channel region, a floating gate, a control gate, and an inter-gatedielectric region between the floating gate and the control gate. Thefloating gate may gave a first region formed from P semiconductor and asecond region formed from metal. The first region may border the tunneloxide over the channel region.

One embodiment disclosed herein includes a memory array comprising aplurality of non-volatile storage elements over a substrate. Each of thenon-volatile storage elements may include a tunnel oxide over thesubstrate, a floating gate, a control gate, and an inter-gate dielectricregion between the floating gate and the control gate. The floating gatemay have a first region formed from P− semiconductor and a second regionformed from metal. The first region of the floating gate may border thetunnel oxide. The second region of the floating gate may border theinter-gate dielectric.

One embodiment disclosed herein includes a method for forming a memoryarray, which may include the following. Transistors and non-volatilestorage elements are formed. An individual transistor may have a gateand a gate oxide. Forming the non-volatile storage elements may includeforming a tunnel oxide over a region for a channel in a substrate;forming a floating gate over the tunnel oxide; forming a control gate;and forming an inter-gate dielectric between the second region of thefloating gate and the control gate. The floating gate may have a firstregion formed from P− semiconductor and a second region formed frommetal, with first region bordering the tunnel oxide over the channelregion.

In one embodiment, forming the transistors and forming non-volatilestorage elements includes the following. A P− semiconductor region isformed over an insulator in one or more first regions in which thenon-volatile storage elements and in one or more second regions in whichthe transistors are to be formed. A metal region is formed over the P−semiconductor region in the one or more first regions and in the one ormore second regions. Portions of the metal are etched away where thetransistor gates are to be formed in the one or more second regions. TheP− semiconductor region is counter-doped where transistor gates are tobe formed to form an N+ semiconductor region for each of the transistorgates. Floating gates are formed in the one or more first regions fromthe P− semiconductor region and the metal region that remains in the oneor more first regions, wherein the insulator serves as the tunnel oxide.Transistor gates are formed in the one or more second regions, whereineach transistor gate includes at least the respective N+ semiconductorregion, the insulator serves as the gate oxide.

In one embodiment, forming the transistors and forming non-volatilestorage elements includes the following. An N+ semiconductor region isformed over an insulator in one or more first regions in which thenon-volatile storage elements and in one or more second regions in whichthe transistors are to be formed. An etch stop layer may be formed overthe N+ region. A second semiconductor region is formed over the n+semiconductor region in the one or more first regions and in the one ormore second regions. Portions of the second semiconductor region areremoved where the floating gates are to be formed in the one or morefirst regions to form openings. The lowest portions of the floatinggates may be counter-doped to convert the n+ semiconductor to p−. Theopenings are filled with metal. The floating gates are formed in the oneor more first regions from the first semiconductor region and the metal.The transistor gates are formed in the one or more second regions, thetransistor gates including at least portions of the second semiconductorregion.

The foregoing detailed description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit embodiments to the precise form disclosed. Many modifications andvariations are possible in light of the above teaching. The describedembodiments were chosen in order to best explain principles andpractical applications, to thereby enable others skilled in the art tobest utilize the various embodiments and with various modifications asare suited to the particular use contemplated. It is intended that thescope of embodiments be defined by the claims appended hereto.

1. A non-volatile storage element comprising: a channel region in asubstrate; a tunnel oxide over the channel region; a floating gate overthe tunnel oxide, the floating gate having a first region formed from Psemiconductor and a second region formed from metal, the first regionborders the tunnel oxide over the channel region; a control gate; and aninter-gate dielectric region between the second region of the floatinggate and the control gate.
 2. The non-volatile storage element of claim1, wherein the first region is P−.
 3. The non-volatile storage elementof claim 1, wherein the first region has a doping concentration suchthat the first region is inverted near the tunnel oxide when an erasevoltage is applied to the control gate.
 4. The non-volatile storageelement of claim 1, wherein the floating gate has a P−/metal junction.5. The non-volatile storage element of claim 1, wherein the metalincludes one or more of W, WN, TiN, TaN, Mo, and TiO.
 6. Thenon-volatile storage element of claim 1, wherein the floating gate hasan upper portion and a lower portion, the first region occupiessubstantially all of the lower portion, the second region occupiessubstantially all of the upper portion.
 7. The non-volatile storageelement of claim 1, wherein the channel region is an n-channel.
 8. Amemory array comprising: a plurality of non-volatile storage elementsover a substrate, each of the non-volatile storage elements including: atunnel oxide over the substrate; a floating gate over the tunnel oxide,the floating gate having a first region formed from P− semiconductor anda second region formed from metal, the first region of the floating gateborders the tunnel oxide; a control gate; and an inter-gate dielectricbetween the second region of the floating gate and the control gate. 9.The memory array of claim 8, further comprising one or more managementcircuits coupled to the plurality of non-volatile storage elements, theone or more management circuits apply an erase voltage to the controlgate of a first of the plurality of non-volatile storage elements, thefirst region has a doping concentration such that the first region isinverted near the tunnel oxide when the erase voltage is applied to thecontrol gate.
 10. The memory array of claim 8, further comprising one ormore management circuits coupled to the plurality of non-volatilestorage elements, the one or more management circuits apply a programvoltage to the control gate of a first of the plurality of non-volatilestorage elements, the first region is not depleted near the tunnel oxidewhen the program voltage is applied.
 11. The memory array of claim 8,further comprising a plurality of transistors, each of the transistorshaving a gate, a channel, and a transistor gate oxide over the channel,the transistor gate having an N+ region bordering the transistor gateoxide.
 12. The memory array of claim 8, wherein the floating gate has anupper portion and a lower portion, the first region occupiessubstantially all of the lower portion, the second region occupiessubstantially all of the upper portion.
 13. A method for forming amemory array comprising: forming transistors, an individual transistorhaving a gate and a gate oxide; and forming non-volatile storageelements, forming the non-volatile storage elements includes: forming atunnel oxide over a region for a channel in a substrate; forming afloating gate over the tunnel oxide, the floating gate having a firstregion formed from P− semiconductor and a second region formed frommetal, the first region borders the tunnel oxide over the channelregion; forming a control gate; and forming an inter-gate dielectricbetween the second region of the floating gate and the control gate. 14.The method of claim 13, wherein the forming transistors and the formingnon-volatile storage elements includes: forming a P− semiconductorregion over an insulator in one or more first regions in which thenon-volatile storage elements and in one or more second regions in whichthe transistors are to be formed; forming a metal region over the P−semiconductor region in the one or more first regions and in the one ormore second regions; forming the floating gates for the non-volatilestorage elements in the one or more first regions from the P−semiconductor region and the metal region that remains in the one ormore first regions, the insulator serves as the tunnel oxide; andforming the transistor gates in the one or more second regions, thetransistor gates including at least the metal and the P− semiconductorregion, the insulator serves as the gate oxide.
 15. The method of claim13, wherein the forming transistors and the forming non-volatile storageelements includes: forming a P− semiconductor region over an insulatorin one or more first regions in which the non-volatile storage elementsand in one or more second regions in which the transistors are to beformed; forming a metal region over the P− semiconductor region in theone or more first regions and in the one or more second regions; etchingaway portions of the metal where the transistor gates are to be formedin the one or more second regions; counter-doping the P− semiconductorregion where transistor gates are to be formed to form an N+semiconductor region for each of the transistor gates; forming thefloating gates in the one or more first regions from the P−semiconductor region and the metal region that remains in the one ormore first regions, the insulator serves as the tunnel oxide; andforming the transistor gates in the one or more second regions, eachtransistor gate including at least the respective N+ semiconductorregion, the insulator serves as the gate oxide.
 16. The method of claim15, further comprising: forming polysilicon in the etched away portionsof the metal where the transistor gates are to be formed in the one ormore second regions and over the metal in the one or more first regions,wherein an individual transistor gate is formed from a portion of thepolysilicon and one of the N+ semiconductor regions.
 17. The method ofclaim 16, further comprising: forming control gates for the non-volatilestorage elements from the polysilicon.
 18. The method of claim 15,further comprising: forming metal in the etched away portions of themetal where transistor gates are to be formed in the one or more secondregions and over the metal in the one or more first regions, wherein thetransistor gates are formed from the metal and the N+ semiconductorregion.
 19. The method of claim 13, wherein the forming transistors andthe forming non-volatile storage elements includes: forming a firstsemiconductor region over an insulator in one or more first regions inwhich the non-volatile storage elements and in one or more secondregions in which the transistors are to be formed, the firstsemiconductor region is n+; forming a second semiconductor region overthe first semiconductor region in the one or more first regions and inthe one or more second regions; removing the second semiconductor regionwhere the floating gates are to be formed in the one or more firstregions to form openings; counter-doping the first semiconductor regionin regions where floating gates are being formed to convert the firstsemiconductor region to p− where floating gates are being formed;filling the openings with metal; forming the floating gates in the oneor more first regions from the first semiconductor region and the metal;and forming the transistor gates in the one or more second regions, thetransistor gates including at least portions of the second semiconductorregion.
 20. The method of claim 19, further comprising: forming an etchstop between the first semiconductor region and the second semiconductorregion in the one or more first regions and in the one or more secondregions.